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TPS70102PWPR 데이터시트(PDF) 7 Page - Texas Instruments

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부품명 TPS70102PWPR
상세설명  Dual-Output Low Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems
PDF  42 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TPS70102PWPR 데이터시트(HTML) 7 Page - Texas Instruments

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background image
UVLO1
Comp
+
-
+
-
+
-
+
-
Thermal
Shutdown
2.5V
+
-
Current
Sense
Reference
Vref
Vref
ENA_1
FB1
ENA_1
120ms
Delay
0.95xVref
FB2
Current
Sense
+
-
ENA_2
ENA_2
Vref
VIN1 (2Pins)
GND
EN
VIN2 (2Pins)
SEQ
(seeNoteB)
PG1
MR2
RESET
VIN1
MR1
VIN1
RisingEdge
Deglitch
Reset
Comp
VOUT2 (2Pins)
FallingEdge
Deglitch
0.83 x Vref
FB2
V
UVComp
OUT2
FallingEdge
Deglitch
0.83 x Vref
FB1
V
UVComp
OUT1
Power
Sequence
Logic
ENA_1
ENA_2
VIN1
10kW
VSENSE1
(seeNoteA)
V
(2Pins)
OUT1
VSENSE2
(seeNoteA)
10kW
0.95xVref
FB1
RisingEdge
Deglitch
PG
Comp
+
-
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
www.ti.com
SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010
DEVICE INFORMATION
Fixed Voltage Version
A.
For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the
device. For other implementations, refer to SENSE terminal connection discussion in the Application Information
section.
B.
If the SEQ terminal is floating at the input, VOUT2 powers up first.
Copyright © 1999–2010, Texas Instruments Incorporated
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