LM5032MTCSLASHNOPB datasheet(24/34 Pages) TI

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osc

17100

0.001 (F

400)

0.001 (246

400)

69.67k

246

LM5032

SNVS344B – MARCH 2005 – REVISED DECEMBER 2014

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Typical Application (continued)

Figure 29. Evaluation Module Schematic

8.2.1 Design Requirements

DESIGN PARAMETERS

VALUE

Input voltage range, VIN

18 V to 45 V

Output voltage, VOUT

48 V

Output current, IOUT

4 A

Output ripple voltage, VRIPPLE(OUT)

< 2% (960 mVpp)

Switching frequency, FSW (per

123 kHz

phase)

8.2.2 Detailed Design Procedure

8.2.2.1 Oscillator Frequency and Maximum Duty Cycle

The LM5032 oscillator frequency should be set at twice the target switching frequency of each interleaved power

stage, for example, Fosc = 2 x Fsw.

From Equation 1, the required value of resistor on the RT pin (R9 in Figure 29) is calculated as follows:

(12)

The nearest E96 value of 69.8 k

Ω is used.

The maximum duty cycle is set to 80% (see the Output Duty Cycle section) by choosing the same value resistor

on the DCL pin, so R30 is also set to 69.8 k

Ω.

8.2.2.2 Power Stage Design

8.2.2.2.1

Boost Inductor Selection

Maximum and minimum operating duty cycles are calculated at maximum and minimum input voltage, where Vd

is the boost diode forward voltage drop, and Vsw(on) is the voltage drop across the boost MOSFET plus current

sense element:

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