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HDV24VL 데이터시트(PDF) 2 Page - AMIC Technology |
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HDV24VL 데이터시트(HTML) 2 Page - AMIC Technology |
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2 / 18 page ![]() © 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 2 of 2 SRAM Arbitration Interrupt Semaphore Logic Block Diagram of Dual Port Static RAM 4K x 16 I/O Control Address Decoder I/O Control Address Decoder BUSY SEM INTF W R/ UB OE LB W R/ OE CE CE S M/ I/O 8-15 I/O 0-7 A 11 A 0 BUSY SEM INTF W R/ UB OE LB CE I/O 8-15 I/O 0-7 A 11 A 0 W R/ OE CE L L L L L L L L L L R R R R R R R R R R L L L L L R R R R R (1) (1) (1) Figure 2. Device Architecture |
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