LP62S161024 Series

PRELIMINARY

(November, 2014, Version 0.0)

3

AMIC Technology, Corp.

Pin Configurations

TSOP (I)

LP62S161024V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A14

A13

A12

A11

A10

A9

A8

NC

WE

CS2

NC

HB

LB

A18

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VCC

GND

BYTE

A16

A15

A19

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

OE

GND

CS1

A0

A17

A7

A6

A5

A4

A3

A2

A1

CSP (Chip Size Package)

48-pin Top View

GND

VCC

A18

A8

A19

A9

A12

A10

A11

NC

A13

A14

A15

GND

VCC

A0

A3

A5

A6

A4

A1

A2

6

5

4

3

2

1

A

B

C

D

E

F

G

H

A17

NC

A7

A16

LB

HB

WE

OE

Note:

The BYTE pin in the 48-pin TSOP (I) package must be tied HIGH to use the device as a 1M x 16 SRAM. The 48-pin TSOP (I)

package can also be used as a 2M x 8 SRAM by tied the BYTE signal LOW. In the 2M x 8 configuration, pin 45 is A20, while