CS5166H datasheet(16/25 Pages) ONSEMI

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CS5166H

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Figure 27. Implementing Shutdown with the CS5166H

CS5166H

IN4148

MMUN2111T1 (SOT−23)

Shutdown

Input

ISENSE

5.0 V

Selecting External Components

The CS5166H buck regulator can be used with a wide

range of external power components to optimize the cost and

performance of a particular design. The following

information can be used as general guidelines to assist in

their selection.

NFET Power Transistors

Both logic level and standard FETs can be used. The

reference designs derive gate drive from the 12 V supply

which is generally available in most computer systems and

utilize logic level FETs. A charge pump may be easily

implemented to permit use of standard FET’s or support

5.0 V or 12 V only systems (maximum of 20 V). Multiple

FET’s may be paralleled to reduce losses and improve

efficiency and thermal management.

Voltage applied to the FET gates depends on the

application circuit used. Both upper and lower gate driver

outputs are specified to drive to within 1.5 V of ground when

in the low state and to within 2.0 V of their respective bias

supplies when in the high state. In practice, the FET gates

will be driven rail to rail due to overshoot caused by the

capacitive load they present to the controller IC. For the

typical application where VCC = 12 V and 5.0 V is used as

the source for the regulator output current, the following

gate drive is provided:

VGS(BOTTOM) + 12 V

VGS(TOP) + 12 V * 5.0 V + 7.0 V

(see Figure 28)

Figure 28. Gate Drive Waveforms Depicting

Rail to Rail Swing

Trace 3− GATE(H) (10 V/div.)

Trace 1− GATE(H) − 5.0 VIN

Trace 4− GATE(L) (10 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Figure 29. Normal Operation Showing the Guaranteed

Non−Overlap Time Between the High and Low−Side

MOSFET Gate Drives, ILOAD = 14 A

Trace 1 = GATE(H) (5.0 V/div.)

Trace 2 = GATE(L) (5.0 V/div.)

The CS5166H provides adaptive control of the external

NFET conduction times by guaranteeing a typical 65 ns

non−overlap (as seen in Figure 29) between the upper and

lower MOSFET gate drive pulses. This feature eliminates

the potentially catastrophic effect of “shoot−through

current”, a condition during which both FETs conduct

causing them to overheat, self−destruct, and possibly inflict

irreversible damage to the processor.

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