Circuit Description

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AX5031

21

5.8.

Framing and FIFO

Most radio systems today group data into packets. The framing unit is responsible for

converting these packets into a bit-stream suitable for the modulator.

The Framing unit supports three different modes:



HDLC



Raw



802.15.4 compliant

The micro-controller communicates with the framing unit through a 32 level  10 bit FIFO. The

FIFO decouples micro-controller timing from the radio (modulator) timing. The bottom 8 bits

of the FIFO contain transmit data. The top 2 bit are used to convey meta information in HDLC

and 802.15.4 modes. They are unused in Raw mode. The meta information consists of packet

begin / end information and the result of CRC checks. The FIFO can be written in power-

down mode.

The FIFO can be operated in polled or interrupt driven modes. In polled mode, the micro-

controller must periodically read the FIFO status register or the FIFO count register to

determine whether the FIFO needs servicing.

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are

is level triggered, active high. Interrupts are acknowledged by removing the cause for the

interrupt, i.e. by emptying or filling the FIFO.

Basic FIFO status (EMPTY, FULL, Overrun, Underrun, and the top two bits of the top FIFO word)

are also provided during each SPI access on MISO while the micro-controller shifts out the

register address on MOSI. See the SPI interface section for details. This feature significantly

reduces the number of SPI accesses necessary.