SM5160DM datasheet(6/7 Pages) NPC

6 / 7 page

NIPPON PRECISION CIRCUITS-6

SM5160CM/DM

Serial data input timing

Serial data input timing is shown in figure 5. Data is

read on the rising edge of CLK. The state on DATA

should be changed in sync with the falling edge of CLK.

LE should be LOW while data is being written to the

shift register. When LE goes HIGH, data is transferred

from the shift register to one of the frequency divider

latches.

Stand-by mode

The stand-by mode is entered by setting VDD1,

VDD2 to 0V while the device is operation.

In the stand-by mode, the amplifiers of XIN, FIN and

N/R counter are stopped. As long as voltage is provide to

VDD3, data written in latch is kept. Exit from this mode

to normal operation, therefore, is made by providing volt-

age to VDD1, VDD2. In this mode, input to FIN must

be done AC coupling, input to XIN must be done AC

coupling or by crystal oscillator. In this mode, DOA,

DOP should be in state of floating.

CLK

DATA

1234

56789

MSB

CONTROL

LSB

Figure 5. Serial data input

SM5160DM 데이터시트(PDF) 6 Page - Nippon Precision Circuits Inc