CS5307GDWR24 datasheet(19/24 Pages) ONSEMI

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CS5307

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As with the output inductor, the input inductor must

support the maximum current without saturating the

inductor. Also, for an inexpensive iron powder core, such as

the −26 or −52 from Micrometals, the inductance “swing”

with DC bias must be taken into account and inductance will

decrease as the DC input current increases. At the maximum

input current, the inductance must not decrease below the

minimum value or the dI/dt will be higher than expected.

5. MOSFET & Heatsink Selection

Power dissipation, package size and thermal requirements

drive MOSFET selection. To adequately size the heat sink,

the design must first predict the MOSFET power

dissipation. Once the dissipation is known, the heat sink

thermal impedance can be calculated to prevent the

specified maximum case or junction temperatures from

being exceeded at the highest ambient temperature. Power

dissipation has two primary contributors: conduction losses

and switching losses. The control or upper MOSFET will

display both switching and conduction losses. The

synchronous or lower MOSFET will exhibit only

conduction losses because it switches into nearly zero

voltage. However, the body diode in the synchronous

MOSFET will suffer diode losses during the non−overlap

time of the gate drivers.

For the upper or control MOSFET, the power dissipation

can be approximated from:

PD,CONTROL + (IRMS,CNTL2 @ RDS(on))

) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)

) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)

(19)

The first term represents the conduction or IR losses when

the MOSFET is ON while the second term represents the

switching losses. The third term is the loss associated with

the control and synchronous MOSFET output charge when

the control MOSFET turns ON. The output losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control FET. The fourth term is the loss

due to the reverse recovery time of the body diode in the

synchronous MOSFET. The first two terms are usually

adequate to predict the majority of the losses.

IRMS,CNTL is the RMS value of the trapezoidal current in

the control MOSFET:

(20)

IRMS,CNTL + D

@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2

ILo,MAX is the maximum output inductor current:

ILo,MAX + IO,MAX 4 ) DILo 2

(21)

ILo,MIN is the minimum output inductor current:

ILo,MIN + IO,MAX 4 * DILo 2

(22)

IO,MAX is the maximum converter output current.

VGATE

VDRAIN

QGD

QGS2

QGS1

VGS_TH

Figure 23. MOSFET Switching Characteristics

D is the duty cycle of the converter:

D + VOUT VIN

(23)

ΔILo is the peak−to−peak ripple current in the output

inductor of value Lo:

DILo + (VIN * VOUT) @ D (Lo @ fSW)

(24)

RDS(on) is the ON resistance of the MOSFET at the

applied gate drive voltage.

Qswitch is the post gate threshold portion of the

gate−to−source charge plus the gate−to−drain charge. This

may be specified in the data sheet or approximated from the

gate−charge curve as shown in the Figure 23.

Qswitch + Qgs2 ) Qgd

(25)

Ig is the output current from the gate driver IC.

VIN is the input voltage to the converter.

fsw is the switching frequency of the converter.

QG is the MOSFET total gate charge to obtain RDS(on).

Commonly specified in the data sheet.

Vg is the gate drive voltage.

QRR is the reverse recovery charge of the lower MOSFET.

Qoss is the MOSFET output charge specified in the data

sheet.

For the lower or synchronous MOSFET, the power

dissipation can be approximated from:

PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))

) (Vfdiode @ IO,MAX 4 @ t_nonoverlap @ fSW)

(26)

The first term represents the conduction or IR losses when

the MOSFET is ON and the second term represents the diode

losses that occur during the gate non−overlap time.

All terms were defined in the previous discussion for the

control MOSFET with the exception of:

(27)

IRMS,SYNCH + 1 * D

@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2

where:

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