SM5843AS1 datasheet(21/24 Pages) NPC

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SM5843A

×1

NIPPON PRECISION CIRCUITS—21

Data Input to Output Delay Timing

This is the digital ﬁlter arithmetic computation time

from the completion of data input at rate fs (tINPUT)

on the rising edge of LRCI to the start of data output

at rate 8fs (tOUTPUT) on the falling edge of WCKO.

Filter response

CKSLN

SYNCN

Mode

tOUTPUT − tINPUT

Filter response 1

LOW (256fs)

LOW

After reset + sync mode

44.625/fs

HIGH

Jitter-free mode

44.25/fs

− 45.0/fs

HIGH (384fs)

LOW

After reset + sync mode

44.75/fs

HIGH

Jitter-free mode

44.375/fs

− 45.125/fs

Filter response 2

LOW (256fs)

LOW

After reset + sync mode

25.625/fs

HIGH

Jitter-free mode

25.25/fs

− 26.0/fs

HIGH (384fs)

LOW

After reset + sync mode

25.75/fs

HIGH

Jitter-free mode

25.375/fs

− 26.125/fs

Figure 12. Delay timing (SYNCN = LOW)

Figure 13. Delay timing (SYNCN = CKSLN = LOW)

44/fs(Filter Response 1)

25/fs(Filter Response 2)

1/fs

Serial data Input

tINPUT

tOUTPUT Serial data output

WCKO

(256fs)

WCKO

(384fs)

LRCI

tOUTPUT

44.625/fs (Filter Response 1)

25.625/fs (Filter Response 2)

tINPUT

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