| 전자부품 데이터시트 검색엔진 |
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MT8972BE 데이터시트(PDF) 3 Page - Mitel Networks Corporation |
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MT8972BE 데이터시트(HTML) 3 Page - Mitel Networks Corporation |
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3 / 20 page ![]() MT8971B/72B 9-109 Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6) Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6) 17 22 OSC1 Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical Characteristics for OSC1 input requirements. 18 23 Precan Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50 k Ω) is provided on this pin. 1,6, 11, 18, 20, 25 NC No Connection. Leave open circuit. 19 24 LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin. 20 26 TEST Test Pin. Connect to VSS for normal operation. 21 27 LIN Receive Signal input (Analog). 22 28 VDD Positive Power Supply (+5V) input. Pin Description (continued) Pin # Name Description DIP PLCC F0 C4 DSTi DSTo F0o B17 B16 B15 B14 B13 B12 B11 B10 B17 B16 B15 B14 B13 B12 B11 B10 B17 B17 Channel Time 0 F0 C4 DSTi DSTo F0o B17 B16 B15 B14 B13 B12 B11 B10 B17 B17 Channel Time 0 B17 B16 B15 B14 B13 B12 B11 B10 B27 B26 B25 B24 B23 B22 B21 B20 B27 B26 B25 B24 B23 B22 B21 B20 Channel Time 16 |
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