Preliminary Information

ISO-CMOS

MT8977

4-119

† Timing is over recommended temperature & power supply voltage ranges.

‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

Figure 15 - DS1 Receive Clock Timing

† Timing is over recommended temperature & power supply voltage ranges.

‡ Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject to production testing.

Figure 16 - ST-BUS Stream Timing

Characteristics

Sym

Min

Max

Units

Test Conditions

1

E1.5i Clock Period

500

648

ns

2

E1.5i Clock Width High or Low

250

324

ns

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Serial Output Delay

125

ns

150 pF load

2

Serial Input Setup Time

15

ns

3

Serial Input Hold Time

50

ns

BIT CELL

BIT CELL

DS1 BIT CELLS FOR

RECEPTION

2.0V

0.8V

E1.5i

Bit Cell Boundaries

C2i

DSTo or

DSTi,

2.0V

0.8V

2.4V

0.4V

2.0V

0.8V

CSTi0/CSTi1

CSTo