PDSP1601 MC

3

FUNCTIONAL DESCRIPTION

The PDSP1601 contains four main blocks: the ALU, the

Barrel Shifter and the two Register Files.

The ALU

The ALU supports 32 instructions as detailed in Table 1.

The inputs to the ALU are selected by the A and B MUXs.

Data will fall through from the selected register through the A

or B input MUXs and the ALU to the ALU output register file in

100ns.

The ALU instructions are latched, such that the instruction

will not start executing until the rising edge of CLK latches the

instruction into the device.

The ALU accepts a carry in from the CI input and supplies

a carry out to the CO output. Additionally, at the end of each

cycle, the carry out from the ALU is loaded into an internal 1

bit register, so that it is available as an input to the ALU on the

next cycle.

In the manner, Multicycle, multiprecisiion

operations are supported. (See MULTICYCLE CASCADE

OPERATIONS).

BFP Flag

The ALU has a user programmable BFP flag. This flag

may be programmed to become active at any one of four

conditions. Two of these conditions are intended to support

Block Floating Point operations, in that they provide flags

indicating that the ALU result is within a factor of two or four of

overflowing the 16 bit number range.

For multiprecision

operations the flag is only valid whilst the most significant 16

bit byte is being processed. In this manner the BFP flag may

be used over any extended word width.

The remaining two conditions detect either an overflow

condition or a zero result. For the overflow condition to be

active the ALU result must have overflowed into the 16th (sign)

bit, (this flag is only valid whilst the most significant 16 bit byte

is being processed). The zero condition is active if the result

from the ALU is equal to zero. For multiprecision operations

the zero flag must be active for all of the 16 bit bytes of an

extended word.

The BFP flag is programmed by executing on of the four

SBFXX instructions (see Table 1). During the execution of any

of these four instructions, the output of the ALU is forced to

zero.

Multicycle/Cascade Operation

The ALU arithmetic instructions contain two or three

options for each arithemtic operation.

The ALU is designed to operate with two's complement

arithmetic, requiring a one to be added to the LSB for all

subtract operations. The instructions set includes instructions

that will force a one into the LSB, e.g. MIAX1, AMBX1, BMAX1

(see Table 1).

These instructions are used for the least significant 16 bits

of any subtract operation.

The user has an option of cascading multiple devices, or

multicycling a single device to extend the arithmetic precision.

Should the user cascade multiple devices, then the cascaded

arithmetic instructions using the external CI input should be

employed for all but the least significant 16 bits, e.g. MIACI,

APBCI, BMACI (see Table 1).

Should the user multicycle a single device, then the

Multicycle Arithmetic instructions, using the internally

registered CO bit should be employed for all but the least

significant 16 bits, e.g. MIACO, APBCO, AMBCO, BMACO

(see Table 1).

16

A INPUT

A REG

A MUX

BFP

AB

B MUX

MSA0-1

2

MSB

IA0-4

5

ALU

CI

CO

RAD-2

3

ALU REG FILE

LEFT REG.

RIGHT REG.

C MUX

MSC

OE

COUT

16

SHIFTER REG FILE

LEFT REG.

RIGHT REG.

RS0-2

3

BARREL SHIFTER

SHIFT

CONTROL

SVOE

IS0-3

SV0-3

S MUX

MSS

B REG

CEB

B INPUT

16

CEA

Fig.2 PDSP1601 block diagram