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PDSP16116MCGGDR 데이터시트(PDF) 12 Page - Mitel Networks Corporation |
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PDSP16116MCGGDR 데이터시트(HTML) 12 Page - Mitel Networks Corporation |
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12 / 17 page ![]() PDSP16116 12 CLK INPUT DATA X AND Y OUTPUT P PORTS OUTPUT SFTA1:0 VALID DATA INPUT CONTROLS CEX AND CEY tCP tDS tDH tCLK tCLKH tCLKL tCSFTA tCSFTA VALID DATA tCONS tCES tCEH tCONH tWS tWH INPUT CONTROLS CONX AND CONY INPUT CONTROL WTB1:0 Fig. 9 Normal mode timing OER AND OEI OUTPUT P PORTS HIGH Z tOPLZ tOPZL HIGH Z tOPZH tOPHZ HIGH Z Fig. 10 Output tristate timing VH 0·5V Delay from output high to output high Z (tOPHZ) 0·5V 0·5V 0·5V VL 1·5V 1·5V Delay from output low to output high Z (tOPLZ) Delay from output high Z to output low (tOPZL) Delay from output high Z to output high (tOPZH) Test Waveform measurement level VH is the voltage reached when the output is driven high VL is the voltage reached when the output is driven low VT = 0V VT = VDD Three state delay measurement load VT DUT 30p 1·5k Fig. 11 Three state delay measurement |
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