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PDSP16256 데이터시트(PDF) 18 Page - Mitel Networks Corporation |
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PDSP16256 데이터시트(HTML) 18 Page - Mitel Networks Corporation |
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18 / 28 page ![]() PDSP16256 18 RES must be held low for 16 cycles BUSY goes active Coefficient loading may start once BUSY has returned low 1234567 16 17 37 38 39 DEVICE RESET SCLK RES BUSY 1234567 BYTE WIDE COEFFICIENT LOAD 8 67 68 69 70 71 00 01 00 01 02 03 3E 3F 00 AC 10 00 20 00 00 02 Control register loaded with CCS high Blank cycles Coefficients loaded into the required address location. This example uses byte wide loading (BYTE held low). CS must be maintained for two cycles SCLK CCS A7:0 C15:0 CS WEN Control register loaded with CCS high Blank cycles Coefficients loaded into the required address location. This example uses word wide loading (BYTE held high). WEN 1234567 WORD WIDE COEFFICIENT LOAD 8 34 35 36 37 38 00 01 02 03 1E 1F AC00 0020 0030 0040 0050 001F 0200 SCLK CCS A7:0 C15:0 CS 00 0010 04 1234567 START OF FILTER OPERATION 8 916 17 18 19 0010 0000 0090 0001 SCLK FEN DA15:0 F31:0 CLKOP 0020 0030 0040 0050 00A0 0001 0004 0004 0000 0000 0000 0000 0000 0000 0000 0000 0000 The first data sample is read as FEN goes high The first result available. CLKOP indicates the first active result cycle Figure. 19 Device startup timing diagrams |
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