PDSP1601/PDSP1601A

3

Symbol

MSB

MSS

B15 - B0

CEB

CLK

MSA0 - MSA1

A15 - A0

CEA

MSC

IS0 - IS3

SV0 - SV3

SVOE

RS0, RS1

RS2

C0 - C15

OE

BFP

CO

RA0 - RA2

CI

IA0 - IA3

IA4

Vcc

GND

Description

of CLK.

of CLK.

B Port data input. Data presented to this port is latched into the input register on the rising

edge of CLK. B15 is the MSB.

Clock enable, B Port input register. When low the clock to this register is enabled.

Common clock to all internal registered elements.

All registers are loaded, and outputs

change on the rising edge of CLK.

edge of CLK.

A Port data input. Data presented to this port is latched into the input register on the rising

edge of CLK. A15 is the MSB.

Clock enable, A Port input register. When low the clock to this register is enabled.

of CLK.

rising edge of CLK.

Shift Value I/O Port. This port is used as an input when shift values are supplied from

external sources, and as an output when Normalise operations are invoked. The I/O functions

are determined by the IS0 - IS3 instruction inputs, and by the

SVOE control.

The shift value is latched internally on the rising edge of CLK.

SV Output enable. When high the SV port can only operate as an input. When low the SV

port can act as an input or as an output, according to the IS0 - IS3 instruction. This pin should

be tied hihg or low, depending upon the application.

rising edge of CLK.

C Port data output. Data output on this port is selected by the C output multiplexer.

C15 is the MSB.

Output enable. The C Port outputs are in high impedance condition when this control is high.

Block Floating Point Flag from ALU, active high.

Carry out from MSB of ALU.

edge of CLK.

Carry in to LSB of ALU.

edge of CLK.

+5V supply: Both Vcc pins must be connected.

0V supply: Both GND pins must be connected.

PIN DESCRIPTIONS

NOTES

1.

All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.