PDSP16488AC datasheet(14/33 Pages) MITEL

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cease when the value in the counter equals that

contained in these bits. The bits are redundant in a

Single device which only uses one 128-byte block.

BITS 6:4 These bits define one of the five basic configurations.

The line delays will automatically be configured to

match the chosen window size and pixel accuracy.

The maximum clock rate that is available to the user

reflects the internal multiplication factor.

BIT 7

This bit must be set if the pixel clock is greater than

20MHz. It disables the output and input time

multiplexing, and instead outputs the least significant

half of the 32-bit intermediate sum for the complete

clock cycle. When the gain control is used, the output

multiplexing will automatically be disabled.

BIT 0

This bit defines the input for the second group of line

delays. It must be set in the 16-bit pixel modes, and

is set by power on reset.

BIT 2:1

These bits control the mode of operation of the line

stores. In real time systems pixels can be stored

either until HRES (sync) goes high , or until a pre-

determined count is reached. In the frame store

mode line store operations are continuous, with a

pre-determined line length.

BIT 3

When this bit is set four pipeline delays are added to

the pixel inputs to compensate for the internal/

external delays between line stores. The extra delay

is only necessary when a device supplied with

system video in which the first pixel in a line is valid

in the period following the first active clock edge. See

Fig 7. The delay is not necessary if the device is fed

from the output of another convolver. When set this

bit will add four additional delays to those defined by

BIT 4

When this bit is set the expansion adder will not be

used. It is automatically set in a Master or Single

device.

EPROM control lines

X7:0

8 bit data from the EPROM to the Master or Single

device. Otherwise data is received from the previous

device in the chain.

X14:8

Lower 7 address bits to the EPROM from a Master or

Single device. Otherwise an input from the data

output of the previous device.

X15

Tied to ground on a Master device to indicate the

EPROM mode.

Tied low on all devices.

An output from a Master or Single device which

provides a data strobe for the other devices. A pullup

resistor is required on this pin in EPROM mode

CS3: 0

Four additional address bits for the EPROM which are

provided by the Master device. They allow 16 addi-

tional devices to be used and must be externally

decoded to provide chip enables.

An input on the Master device which is driven from

the PC1 output of the last device in the chain. Used

internally to terminate the write strobe. Connected

to previous PC1 outputs at intermediate points in

the chain. Not needed for a Single device.

An output connected to the PC0 input of the next

device in the chain. The last device feeds back to the

Master. Not needed for a Single device.

An enable which is produced by decoding CS3:0 from

the Master. It is not needed for a Master or Single

device which will always use the bottom block of

addresses with internally generated write strobes. It

can, however, be used on these devices to initiate a

new load procedure after the initial power-on

sequence.

An active low signal produced by an EPROM sup-

ported Master or Single device. An input to all other

devices. It indicates that a register load sequence

is occurring, either after power on, or as the result

of CE as explained above. It remains active until

devices. A pullup resistor is required on this pin in

EPROM mode.

System Configuration

The device is configured using a combination of the state of

the SINGLE and MASTER pins, and the contents of the four

Mode Control registers. In a Master or Single device the state of

the X15 pin is used to define whether the system is EPROM or

Host supported, as described above.

Mode Control Registers

BITS 3:0 These bits are ‘don’t care’ when using a host compu-

ter but to a Master device, in an EPROM supported

system, they define the number of interconnected

chips. The EPROM must contain contiguous 128 byte

blocks for each of the devices in the system and a 4-

bit counter in the Master device will sequence through

up to 16 block reads. An internal comparator in the

Master causes the loading of the internal registers to

PC0

PC1

PROG

Function

Number of extra devices from 1-15

8-bit, 8 8 window, 10MHz max.,

8 512 line delays.

16-bit, 8 4 window, 10MHz max.,

4 512 line delays.

16-bit, 4 4 window, 20MHz max.,

4 512 line delays.

8-bit, 8 4 window, 20MHz max.,

4 1024 line delays.

8-bit, 4 4 window, 40MHz max.,

4 1024 line delays

Multiplexed exp. data

Non-multiplexed exp. data

Code

XXXX

000

001

010

011

101

Bit

3:0

6:4

Table 8 Register A bit functions

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