3

SP8858

Fig. 2 SP8858 block diagram

FREQUENCY (MHz)

500

400

300

200

100

50

0

0

500

750

1000

1500

80

TYPICAL

SENSITIVITY

GUARANTEED

OPERATING

WINDOW

GUARANTEED

OPERATING

WINDOW

Fig. 3 Typical input characteristics and input drive requirements

11

A

COUNTER

F1/F2 22-BIT DATA BUFFER

M

COUNTER

24-BIT SHIFT REGISTER

16-BIT REFERENCE BUFFER

DATA

INTERFACE

16/17 OR 8/9

PHASE

DETECTOR

R

DIVIDER

BUFFER

LOCK

DETECT

RF INPUT

10

F1/F2

DATA

CLOCK

ENABLE

POWER

DOWN

13

14

15

16

6

RPD

24

27

CP OUTPUT

25

20

21

CRYSTAL

5

4

sense bit in the F1/F2 programming word. The pin allocations

shown are correct when the sense bit is low (see Fig. 6).

RF INPUT

C1 C2

XFV

FV

RESET

15 BITS

4 BITS

3 BITS

SELECT F1/F2

ACTIVE A

LSB

MSB

22 BITS

SELECT MODULUS

16 BITS

SELECT R

13 BITS

PD GAIN

2 BITS

XFR

FR

DECODE

PD1

PD2

FV

XFV

FR

XFR

CHARGE

PUMP

PD

SENSE

DISABLE

CP REF

25

LOCK

DETECT

CD

28

MODULUS CONTROL