VP211

6

Layout And Grounding

As with all high speed A to D converters, careful

consideration must be given to the PCB layout. High

performance can be obtained from the VP211 by tying all

grounds to a solid low impedance ground plane. Separate

analog and digital ground planes with a single common link

under the device can also be used to help reduce the

amount of digital noise fed back into the analog section of the

converter.

The VP211 should be decoupled with low impedance

100nF ceramic capacitors close to the package pins to avoid

lead inductance effects and the decoupling on supply lines

should further be improved by using a 47

µF tantalum

capacitor in parallel with a 100nF ceramic capacitor. If VCCA

is derived from VCCD, a small inductor should be used to

reduce digital noise on the analog power supply. Jitter and

noise on clock input pins must be minimised. Long clock

lines should therefore be avoided and all clock lines correctly

terminated. Cross talk of digital signals to the analog inputs

must also be prevented as sampling cross talk produces DC

offsets on the sampled data, for this reason analog inputs

should not be run next to clock or data lines. Device

connections to the ground plane should be as short as

possible.

Application Circuit

Fig.5 shows a typical applications circuit for the VP211.

The supply connections are made using separate low noise

digital and analog power supplies and VCCD is further

isolated from VCCO using a 1.2

µH inductor.

The COMPA and COMPB pins must be decoupled to

reduce any ripple at low frequencies which may distort the

ADC driver amplifier output, (see Fig.2.) The decoupling

capacitor value is determined by the required low frequency

performance of the system and can be obtained from the

following equation.

A ripple voltage

≤ 10mV is recommended for good

10KHz a value of 0.75

µF is required for C

To

ensure

effective

A.C.

coupling

at

low

input

frequencies, the coupling capacitors on pins 6 and 11 can be

calculated from the high pass filter corner frequency

equation,

where

(R = Input Resistance, 25K typ. - 20K min)

1

2 x

Fig.5 Applications diagram

VP211

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Analog Ground

Digital Ground

A Channel

Data

B Channel

Data

CLKIN

VINA

VCCA

VINB

1.2

µH

47

µ

47

µ

100n

100n

100n

100n

50R

50R

50R

100n

VCCD

100n

100n

100n