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CS4328 데이터시트(PDF) 26 Page - Cirrus Logic

부품명 CS4328
상세설명  18-Bit, Stereo D/A Converter for Digital Audio
PDF  31 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4328 데이터시트(HTML) 26 Page - Cirrus Logic

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the trace at the SDATA BNC connector and
place a jumper between the SDATA BNC and
U8 pin 11. CMODE is set LOW for a master
clock of 256 times the sample rate.
P7 must
have both the internal and external jumpers in-
stalled. This will route the master clock to the
E XT C LK IN B NC fo r co nn ec tion to the
CDB4328 MCLK.
If a CS5336/8 is installed an additional modifi-
cation is required to invert the SCLK prior to
transmission to the CDB4328. This can be im-
plemented as follows: cut the trace at the SCLK
BNC and install a jumper between U7 pin 4 and
the SCLK BNC.
CDB5336/7/8/9 and CDB4328 Interconnection
for Method 2
Shielded coaxial cables with BNC connectors
should be used to make the following connec-
tions: L/R to L/R, SCLK to SCLK, SDATA to
SDATA, EXTCKIN to MCLK.
CDB4328 Interfacing to the CDB5326/7/8/9
A method of interfacing the CDB5326/7/8/9 and
the CDB4328 requires a direct interface through
the EXTCLKIN, SCLK, SDATA, and L/R BNC
connectors.
This technique requires modifica-
tions to the CDB5326/7/8/9 to derive the proper
clock frequencies.
This is done by utilizing a
12.288 MHz clock and supplying a clock to the
CDB5326/7/8/9 at 6.144 MHz.
CDB4328 Configuration
The CS4328 must be set to receive data in for-
mat 2 (DIF1 high and DIF0 low). Modify the
jumpers located near pins 12 and 13 of the
CS4328. JP2 sets the clock to sample frequency
ratio (CKS) on the CS4328 and is set low for a
256 ratio.
JP3 selects the source of SDATA, SCLK and L/R
that will be provided to the converter and should
be removed to access the multiple clocks from
the CDB5326/7/8/9. Remove the 12.288 MHz
oscillator (U8).
CDB5326/7/8/9 Configuration
Remove the clock source jumper (P2). Remove
the 6.144 MHz oscillator (U2) and replace with
the 12.288 MHz oscillator from the CDB4328.
Install a divide by 2 functi on on the
CDB5326/7/8/9 digital patch area. Use a
74HC74 with the D input connected to the Q
output. Connect the oscillator output to the
74HC74 clock input. Connect the Q output to
U1 pin 23.
Position P2 to connect the oscillator output to
the EXTCLKIN.
CDB5326/7/8/9 and CDB4328 Interconnection
Shielded coaxial cables with BNC connectors
should be used to make the following connec-
tions: L/R to L/R, SCLK to SCLK, SDATA to
SDATA, EXTCLKIN to MCLK.
CDB4328
DS62DB2
27



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