PIC16F84A-04SLASHP datasheet(15/68 Pages) MICROCHIP

15 / 68 page

PIC16F84A

Preliminary

DS35007A-page 15

3.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (=1) will make the corresponding PORTB pin

an input, i.e., put the corresponding output driver in a

hi-impedance mode. Clearing a TRISB bit (=0) will

make the corresponding PORTB pin an output, i.e., put

the contents of the output latch on the selected pin.

EXAMPLE 3-1:

INITIALIZING PORTB

BCF

STATUS, RP0

;

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

BSF

STATUS, RP0

; Select Bank 1

MOVLW

0xCF

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION<7>). The weak

pull-up is automatically turned off when the port pin is

conﬁgured as an output. The pull-ups are disabled on a

Power-on Reset.

FIGURE 3-3:

BLOCK DIAGRAM OF PINS

RB7:RB4

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e. any RB7:RB4 pin con-

ﬁgured as an output is excluded from the interrupt on

change comparison). The input pins (of RB7:RB4) are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB7:RB4 are

OR’ed together to generate the RB Port Change Inter-

rupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the inter-

rupt in the following manner:

Any read or write of PORTB. This will end the

mismatch condition.

Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 3-4:

BLOCK DIAGRAM OF PINS

RB3:RB0

RBPU(1)

Data Latch

From other

VDD

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

Note

1: TRISB = '1' enables weak pull-up

(if RBPU = '0' in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

I/O

pin(2)

RBPU(1)

I/O

pin(2)

Data Latch

VDD

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

RB0/INT

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note

1: TRISB = '1' enables weak pull-up

(if RBPU = '0' in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

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