DS39566A-page 2

Advance Information

 2002 Microchip Technology Inc.

TABLE 2:

SPECIAL FUNCTION REGISTER SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

Bank 2

INDF

0000 0000

101h

TMR0

Timer0 Module’s Register

xxxx xxxx

uuuu uuuu

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

STATUS

IRP

RP1

RP0

TO

PD

ZDC

C

0001 1xxx

000q quuu

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

uuuu uuuu

105h

—

Unimplemented

—

—

106h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

107h

—

Unimplemented

—

—

108h

—

Unimplemented

—

—

109h

—

Unimplemented

—

—

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

10Ch

PMDATL

Data Register Low Byte

xxxx xxxx

uuuu uuuu

10Dh

PMADRL

Address Register Low Byte

xxxx xxxx

uuuu uuuu

10Eh

PMDATH

—

—

Data Register High Byte

xxxx xxxx

uuuu uuuu

10Fh

PMADRH

—

—

—

Address Register High Byte

xxxx xxxx

uuuu uuuu

Bank 3

INDF

0000 0000

181h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

PCL

Program Counter's (PC) Least Significant Byte

0000 0000

0000 0000

STATUS

IRP

RP1

RP0

TO

PD

ZDC

C

0001 1xxx

000q quuu

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

uuuu uuuu

185h

—

Unimplemented

—

—

186h

TRISB

PORTB Data Direction Register

1111 1111

1111 1111

187h

—

Unimplemented

—

—

188h

—

Unimplemented

—

—

189h

—

Unimplemented

—

—

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

---0 0000

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

18Ch

PMCON1

—

—

—

—

—

—

RD

1--- ---0

1--- ---0

18Dh

—

Unimplemented

—

—

18Eh

—

Reserved maintain clear

0000 0000

0000 0000

18Fh

—

Reserved maintain clear

0000 0000

0000 0000

Legend:

x

= unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note

1:

These registers can be addressed from any bank.

2:

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3:

Other (non power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.

4:

This bit always reads as a ‘1’.