SM8750AV

NIPPON PRECISION CIRCUITS—2

BLOCK DIAGRAM

PIN DESCRIPTION

Number

Name

I/O

Description

1

S TA R T

I

Measurement star t control. Phase difference to voltage conversion starts on the falling edge.

2

D ATA

I

Tw o-valued signal input

3

CALMON

O

Internal calibration state signal monitor output. N-channel open drain. Active when calibrated.

4

RDCLK

I

PLL clock input

5

LIMIT

I

T V OUT output voltage-limit control voltage input

6

SENB

I

Ser ial interface: enable signal input

7

SCLK

I

Ser ial interface: clock signal input

8

S D ATA

I/O

Ser ial interface: data signal input/ack n owledge signal output. N-channel open drain.

9

G N D

–

Ground

1 0

R D ATA R

O

D ATA rising edge: delay adjust circuit reference-current setting resistor connection

1 1

R D ATA F

O

D ATA falling edge: delay adjust circuit reference-current setting resistor connection

1 2

RDUTY

O

RDCLK duty adjust circuit reference-current setting resistor connection

1 3

R C P

O

Phase difference to voltage converter coefficient reference-current setting resistor connection

1 4

VREF2

I

2V reference voltage input

1 5

T V O U T

O

Phase difference to voltage converter output

1 6

V D D

–

5V supply

RDATAF

39k

RDUTY

22k

CALMON

Charge pump

output buffer

(phase difference to

voltage converter)

47k

Phase comparator

SCLK

START

DATA

Automatic regulation

controller

Duty correction

Delay correction

VDD TVOUT

RDCLK

VREF2

RCP

33k

Serial interface

to each block

SENB

LIMIT

SDATA GND

RDATAR

39k