AX8052F151 datasheet(39/51 Pages) ONSEMI

39 / 51 page

Transceiver

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AX8052F151

The encoder is programmed using the register

AX5051_ENCODING, details and

recommendations on usage are given in the AX5051 Programming Manual.

6.6. Framing and FIFO

Most radio systems today group data into packets. The framing unit is responsible for converting

these packets into a bit-stream suitable for the modulator, and to extract packets from the

continuous bit-stream arriving from the demodulator.

The Framing unit supports four different modes:

•

HDLC

•

Raw

•

Raw with Preamble Match

•

802.15.4 compliant

The microcontroller communicates with the framing unit through a 4 level × 10 bit FIFO. The FIFO

decouples microcontroller timing from the radio (modulator and demodulator) timing. The bottom

8 bits of the FIFO contain transmit or receive data. The top 2 bit are used to convey meta

information in HDLC and 802.15.4 modes. They are unused in Raw and Raw with Preamble Match

modes. The meta information consists of packet begin / end information and the result of CRC

checks.

The framing unit contains one FIFO. Its direction is switched depending on whether transmit or

receive mode is selected.

The FIFO can be operated in polled or interrupt driven modes. In polled mode, the microcontroller

must periodically read the FIFO status register or the FIFO count register to determine whether the

FIFO needs servicing.

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are

provided. Interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or

filling the FIFO.

To lower the interrupt load on the microcontroller, one of the DMA channels may be instructed to

transfer data between the transceiver FIFO and the XRAM memory. This way, much larger buffers

can be realized in XRAM, and interrupts need only be serviced if the larger XRAM buffers fill or

empty.

AX8052F151 데이터시트(PDF) 39 Page - ON Semiconductor