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CPT112S 데이터시트(PDF) 31 Page - Silicon Laboratories |
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CPT112S 데이터시트(HTML) 31 Page - Silicon Laboratories |
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31 / 35 page ![]() Dimension Min Max Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 8. A 2x2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume. 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 6.3 QFN20 Package Marking 112S TTTT YWW+ Figure 6.3. QFN20 Package Marking The package marking consists of: • 112S – The part number designation. • TTTT – A trace or manufacturing code. The first letter of this code is the hardware revision. • Y – The last digit of the assembly year. • WW – The 2-digit workweek when the device was assembled. • + – Indicates the device is RoHS-compliant. CPT112S Data Sheet QFN20 Package Specifications silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.1 | 30 |
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