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TAS5731MPHPR 데이터시트(PDF) 31 Page - Texas Instruments

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부품명 TAS5731MPHPR
상세설명  Digital Audio Power Amplifier
PDF  81 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TAS5731MPHPR 데이터시트(HTML) 31 Page - Texas Instruments

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23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB
LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19
18
1
19
18
1
0
0
0
15
14
15
14
23
22
1
15
14
MSB
LSB
19
18
1
19
18
1
0
0
0
15
14
15
14
TAS5731M
www.ti.com
SLOS838C – JULY 2013 – REVISED AUGUST 2015
Feature Description (continued)
9.3.10.3 Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-
bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
Figure 52. Right-Justified 64-FS Format
Copyright © 2013–2015, Texas Instruments Incorporated
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