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AD7402

Data Sheet

Rev. A | Page 4 of 20

TIMING SPECIFICATIONS

VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +105°C, unless otherwise noted.

Table 2.

Parameter1

Min

Typ

Max

Unit

Description

fMCLKOUT2

9.4

10.6

MHz

Master clock output frequency

t13

±10

Data access time after MCLKOUT rising edge

t23

Data hold time after MCLKOUT falling edge

Master clock low time

Master clock high time

1 Sample tested during initial release to ensure compliance.

2 Mark space ratio for clock output is 45/55 to 55/45.

3 Defined as the time required for the output to cross 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V, or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V, as

outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance.

Figure 2. Data Timing

1 SEE NOTE 3 OF TABLE 2 FOR FURTHER DETAILS.

MDAT

MCLKOUT

2.0V OR 0.7V × VDD21

0.8V

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