ADS1262 datasheet(39/134 Pages) TAOS

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Conversions (DRDY)

+ 105%

PGAD_ALM bit

Alarms latched during

conversion cycle

- 105%

+105% VREF

VOUTP

VOUTN

PGA

ADC

Digital

Filter

-105% VREF

Conversion

Start Reset

STATUS

DATA 1

DATA 2

DATA 3

DATA 4

PGAD_ALM

Bit 1 of STATUS byte

Latch

VREF Comparators

PGA Output

difference amplifier

Data Bytes

CRC/CHK

ADS1262, ADS1263

www.ti.com

SBAS661B – FEBRUARY 2015 – REVISED JULY 2015

9.3.7.1 PGA Differential Output Monitor

ADC1 incorporates a differential PGA output voltage monitor. This voltage monitor triggers an alarm when the

magnitude of the differential PGA output voltage is more positive than +105% or more negative than –105% of

full scale, but only during a conversion cycle. The alarm event, corresponding to the conversion cycle when the

alarm occurred, is set in the status byte (PGAD_ALM). For the next conversion, the alarm resets. If the

magnitude of differential output voltage is within the range of ±105% of full-scale range, the alarm remains reset.

The PGA differential monitor block diagram is shown in Figure 73.

Figure 73. PGA Differential Overload Monitor

Figure 74 shows an example of the differential overrange monitor event.

Figure 74. PGA Differential Alarm

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