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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DLPC900ZPC 데이터시트(PDF) 63 Page - Texas Instruments |
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DLPC900ZPC 데이터시트(HTML) 63 Page - Texas Instruments |
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63 / 72 page  DLPC900 www.ti.com DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015 10.2 Layout Example The DLP® LightCrafter™ 9000 EVM PCB is targeted at 14 layers with layer stack up shown in Figure 32. The PCB layer stack may vary depending on system design. However, careful attention is required to meet design considerations. Layers 1 and 14 should consist of the components layers. Layers 2, 4, 6, 9, 11,and 13 should consist of solid ground planes. Layers 7 and 8 should consist of solid power planes. Layers 1, 3, 5, 10, 12, and 14 should be used as the primary routing layers. Routing on external layers should be less than 0.25 inches for priority one and two signals. Refer to the Table 21 for signal priority groups. Board material should be FR-370HR or similar. PCB should be designed for lead-free assembly with the stackup geometry shown in Figure 32 and Figure 33. Figure 32. Board Layer Stack Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Links: DLPC900 |
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