SEC2410 datasheet(39/283 Pages) MICROCHIP

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 2013 - 2014 Microchip Technology Inc.

DS00001587C-page 39

SEC2410/SEC4410

The Work Queues for the Processor is different from all other work queues. There is really only a single work queue at

0x00ED00. The Work Queue is 32 bits wide. The address of the WQ is aliased from 0x00ED00 to 0x00EDFF.

AHB

addresses A7 through A3 are mapped to D31 through D27. The format of the data written to the FIFO is given below.

If the processor wants to write to its own work queue, 0x50 must be pre-pended to the address.

6.4.4

WORK QUEUE FIFO EXAMPLE:

Completion Notification to EP Read (CR_AHB+ED00), with Context 0x5, last = 1, Length = 0x777

Actual Data written into FIFO: 0x00077785

Given this value, the Processor can determine the Endpoint number. This way, the Processor can have 16 Read and

16 Write endpoints in a single FIFO. The FIFO is 16 deep. If the FIFO is full when another notification comes in, the write

is suppressed, and the overflow bit is set.

6.5

Bridge Control Registers

These control registers appear on the CR_X32 bus.

TABLE 6-1:

WQE/CN FIFO FORMAT

Bits

Name

Description

D31~D27

WQ ID

AHB Address A[7:3]

D27~D24

Status

Not Used Currently

D23~D8

Length

This length overrides the length in the work request.

For SEC2410/SEC4410, only the lower 12 bits will be used.

Last_buffer

If last_buffer = 1, this indicates that this is the last buffer of the

transaction.

D6~D0

Context[6:0]

This field contains the reference to the Work Request being used.

TABLE 6-2:

WORK QUEUE FIFO

AHB_WQ_FIFO_SLV

(CR_AHB+ED00 RESET=0x00000000)

WQ FIFOSlave Address

Byte

Name

R/W

Description

31:0

CN_DATA

This is the Work Queue FIFO that is written to by the AMBA master

on the CR_AHB bus when it wants to post a completion notification.

TABLE 6-3:

WORK QUEUE FIFO

WQ_FIFO

(CR_X32 + 0x0C30 RESET=0x00000000)

Processor Work Queue FIFO

Byte

Name

R/W

Description

31:0

WQ_DATA

This is the Work Queue FIFO that is read by the Processor to read

the completion notifications posted to it. The FIFO read pointer is

advance every time the most least byte (address 0) is read.

To avoid endianess issues, read this fifo 32bits at a time only

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