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USB4624 데이터시트(PDF) 18 Page - Microchip Technology |
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USB4624 데이터시트(HTML) 18 Page - Microchip Technology |
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18 / 58 page ![]() USB 2.0 HSIC Hi-Speed 4-Port Hub Controller Datasheet DS00001717A-page 18 2014 Microchip Technology Inc. Note 3.2 When the device is configured to enable the HSIC upstream port, the USB Product ID (PID) will be 4624. When the device is configured to enable the USB upstream port, the USB PID will be 4524. Note 3.3 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 6.3, "Device Configuration Straps," on page 30 for additional information. 2 +3.3V Power Supply VDD33 P +3.3V power supply. These pins must be connected to VDDA33. Refer to Chapter 4, "Power Connections," on page 21 for power connection information. 1 +1.8-3.3V Core Power Supply Input VDDCOREREG P +1.8-3.3V core power supply input to internal +1.2V regulator. This pin may be connected to VDD33 for single supply applications when VBAT equals +3.3V. Running in a dual supply configuration with VDDCOREREG at a lower voltage, such as +1.8V, may reduce overall system power consumption. In dual supply configurations, a 4.7 μF (<1 Ω ESR) capacitor to ground is required for regulator stability. The capacitor should be placed as close as possible to the device. Refer to Chapter 4, "Power Connections," on page 21 for power connection information. 1 +1.2V Core Power Supply VDDCR12 P +1.2V core power supply. In single supply applications or dual supply applications where 1.2V is not used, a 1.0 μF (<1 Ω ESR) capacitor to ground is required for regulator stability. The capacitor should be placed as close as possible to the device. Refer to Chapter 4, "Power Connections," on page 21 for power connection information. 3 +1.2V HSIC Power Supply Input VDD12 P +1.2V HSIC power supply input. Refer to Chapter 4, "Power Connections," on page 21 for power connection information. Exposed Pad on package bottom (Figure 3.1) Ground VSS P Common ground. This exposed pad must be connected to the ground plane with a via array. Table 3.1 Pin Descriptions (continued) NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION |
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