USB5534B datasheet(63/73 Pages) MICROCHIP

63 / 73 page

 2012 - 2015 Microchip Technology Inc.

DS00001681C-page 63

USB5534B

7.4

SMBus Timing

The SMBus slave interface complies with the SMBus Specification Revision 1.0. See Section 2.1, AC Specifications on

page 3 for more information.

FIGURE 7-4:

SMBUS SLAVE TIMING DIAGRAM

TABLE 7-3:

SMBUS SLAVE TIMING MODES

Symbol

ParameterMIN

MAX

Unit

fSCL

SM_CLK clock frequency

100

KHz

tHD;STA

Hold time START condition

s

tLOW

LOW period of the SM_CLK clock

4.7

s

tHIGH

HIGH period of the SM_CLK clock

s

tSU;STA

Set-up time for a repeated START condition

4.7

s

tHD;DAT

DATA hold time\

tSU;DAT

DATA set-up time

250

Rise time of both SM_DATA and SM_CLK signals

1000

Fall time of both SM_CLK and SM_DATA lines

300

tSU;STO

Set-up time for a STOP condition

s

tBUF

Bus free time between a STOP and START

condition

4.7

s

SM_DATA

SM_CLK

tBUF

tHD;STA

tSU;STO

tSU;STA

tSU;DAT

tHIGH

tHD;DAT

tHD;STA

tLOW

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