ADS42B49 datasheet(21/65 Pages) TI1

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N+1

N+2

11 Clock Cycles

(1)

Input

Clock

CLKOUTM

CLKOUTP

Output Data

(2)

DxP, DxM

DDR

LVDS

N-11

N-10

N-9

N-8

N-1

N+1

N+2

11 Clock Cycles

(1)

CLKOUT

Output Data

D[13:0]

Parallel

CMOS

Input

Signal

Sample

N+1

N+2

N+3

N+4

tPDI

CLKM

CLKP

N-11

N-10

N-9

N-8

N+11

N+12

N+13

DAn_P

DBn_P

DAn_M

DBn_M

GND

Logic0

(1)

ODL =

350mV

Logic1

(1)

ODH =+350mV

OCM

ADS42B49

www.ti.com

SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015

9 Parameter Measurement Information

(1)

With an external 100-

Ω termination.

Figure 37. LVDS Output Voltage Levels

(1)

The ADC latency after reset is 11 clock cycles. Overall latency = ADC latency + tPDI.

(2)

E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth).

Figure 38. Latency Timing Diagram

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