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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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A6985F3V3 데이터시트(PDF) 51 Page - STMicroelectronics |
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A6985F3V3 데이터시트(HTML) 51 Page - STMicroelectronics |
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51 / 77 page  DocID027738 Rev 2 51/77 A6985F Application notes 77 Figure 39. Slave to master mode transition The external master can force a latched SLAVE mode driving the SYNCH pin low at power- up, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise counts to design the slope compensation. The same considerations above are also valid. The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see Table 5 on page 8 - Synchronization section): Low level < VSYN THL= 0.7 V sinking 5 mA High level > VSYN THH = 1.2 V sourcing 0.7 mA Figure 40. Master driving capability to synchronize the A6985F 250kHz typ. SLAVE mode stand alone operation at nominal fsw SYNCH signal switching node |
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