A6985F5V datasheet(50/77 Pages) STMICROELECTRONICS

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Application notes

A6985F

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DocID027738 Rev 2

accordingly with the frequency of the synchronization signal. The slope compensation

contribution is latched at power-up and so fixed during the device operation.

The A6985F normally operates in MASTER mode, driving the SYNCH line at the selected

oscillator frequency as shown in Figure 35 and Figure 36.

In SLAVE mode the A6985F sets the internal oscillator at 250 kHz typ. (see Table 6 on

page 11 - first row) and drives the line accordingly.

Figure 38. A6985F synchronization driving capability

In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the

normal operation, the external master must drive the SYNCH pin with a clock signal

frequency higher than the maximum oscillator spread (refer to Table 6) for at least 10

internal clock cycles.

For example: selecting RFSW = 0 W to GND

the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it

is able to synchronize to a clock signal in the range 275 kHz - 2 MHz (see Figure 37).

Anyway it is suggested to limit the frequency range within ± 20% fSW resistor nominal

frequency (see details in text below). If not spread spectrum is required, all the regulators

synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the

example).

The device keeps operating in slave mode as far as the master is able to drive the SYNCH

pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes

back into MASTER mode at the nominal oscillator frequency after successfully driving one

pulse at 250 kHz (see Figure 39) in the SYNCH line.

Table 12. Example of oscillator frequency selection from Table 6

Symbol

RVCC (E24 series)

RGND (E24 series)

fSW min.

fSW typ.

fSW max.

fSW



450

500

550

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