SPEAR320S datasheet(92/113 Pages) STMICROELECTRONICS

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Timing requirements

SPEAr320S

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Doc ID 022508 Rev 2

5.11

I2C timing characteristics

The timing characterization is performed using primetime assuming an output load

capacitance of 10 pF on SCL and SDA.

Figure 25.

Output signal waveform for I2C signals

The timings of the high and low level of SCL (tSCLHigh and tSCLLow) are programmable.

The clock-to-output data delay is:

●

MIN (T(clk+data)min) = 5.9

●

MAX (T(clk+data)max) = 15

The timings shown in Figure 25 depend on the programmed value of tSCLHigh and tSCLLow.

The values listed in Table 66 to Table 68 have been calculated using the minimum

programmable values of :

●

High-speed mode: IC_HS_SCL_HCNT= 19 and IC_HS_SCL_LCNT= 53 registers

●

Fast-speed mode: IC_FS_SCL_HCNT= 99 and IC_FS_SCL_LCNT= 215 registers

●

Standard-speed mode: IC_SS_SCL_HCNT= 664 and IC_SS_SCL_LCNT=

780 registers

These minimum values depend on the AHB clock frequency, which is 166 MHz.

Note:

A device may internally require a hold time of at least 300 ns for the SDA signal (referred to

the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL

(Please refer to the I2C Bus Specification v3-0 Jun 2007). However, the SDA data hold time

in the I2C controller of SPEAr320S is one-clock cycle based (6 ns with the HCLK clock at

166 MHz). This time may be insufficient for some slave devices. A few slave devices may not

receive the valid address due to the lack of SDA hold time and will not acknowledge even if

the address is valid. If the SDA data hold time is insufficient, an error may occur.

Workaround: If a device needs more SDA data hold time than one clock cycle, an RC delay

circuit is needed on the SDA line as illustrated in Figure 26.

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