DP83867CS datasheet(85/114 Pages) TI1

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DP83867CS, DP83867IS, DP83867E

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SNLS504 – OCTOBER 2015

9.6.40 Receive Configuration Register (RXFCFG)

This register provides receive configuration for Wake on LAN (WoL).

Table 51. Receive Configuration Register (RXFCFG), Address 0x0134

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:12

RESERVED

0, RO

RESERVED

WOL_OUT_CLEAR

0, RW, SC

Clear Wake on LAN Output:

This bit is only applicable when configured for level mode.

1 = Clear Wake on LAN output

10:9

WOL_OUT_STRETCH

00, RW

Wake on LAN Output Stretch:

If WoL out is configured for pulse mode, the pulse length is defined

as the following number of 125MHz clock cycles:

11 = 64 clock cycles

10 = 32 clock cycles

01 = 16 clock cycles

00 = 8 clock cycles

WOL_OUT_MODE

0, RW

Wake on LAN Output Mode:

1 = Level Mode. WoL is cleared by a write to WOL_OUT_CLEAR

(bit 11).

0 = Pulse Mode. Pulse width is configured via

WOL_OUT_STRETCH (bits 10:9).

ENHANCED_MAC_SUPPORT

0, RW

Enable Enhanced Receive Features:

1 = Enable for Wake on LAN, CRC check, and Receive 1588

indication.

0 = Normal operation.

RESERVED

0, RO

RESERVED

SCRON_EN

0, RW

Enable SecureOn Password:

1 = SecureOn Password enabled.

0 = SecureOn Password disabled.

WAKE_ON_UCAST

0, RW

Wake on Unicast Packet:

1 = Issue an interrupt upon reception of Unicast packet.

0 = Do not issue an interrupt upon reception of Unicast packet.

RESERVED

0, RO

RESERVED

WAKE_ON_BCAST

1, RW

Wake on Broadcast Packet:

1 = Issue an interrupt upon reception of Broadcast packet.

0 = Do not issue an interrupt upon reception of Broadcast packet.

WAKE_ON_PATTERN

0, RW

Wake on Pattern Match:

1 = Issue an interrupt upon pattern match.

0 = Do not issue an interrupt upon pattern match.

WAKE_ON_MAGIC

0, RW

Wake on Magic Packet:

1 = Issue an interrupt upon reception of Magic packet.

0 = Do not issue an interrupt upon reception of Magic packet.

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