DP83867CSRGZR datasheet(45/114 Pages) TI1

45 / 114 page

DP83867CS, DP83867IS, DP83867E

www.ti.com

SNLS504 – OCTOBER 2015

9.6 Register Maps

In the register definitions under the ‘Default’ heading, the following definitions hold true:

Read Write access

RW/SC

ReadWrite access/Self Clearing bit

Read Only access

COR

COR = Clear On Read

RO/COR

Read Only, Clear On Read

RO/P

Read Only, Permanently set to a default value

Latched Low and held until read, based upon the occurrence of the corresponding event

Latched High and held until read, based upon the occurrence of the corresponding event

9.6.1 Basic Mode Control Register (BMCR)

Table 11. Basic Mode Control Register (BMCR), Address 0x0000

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESET

0, RW/SC

Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is re-strapped.

LOOPBACK

0, RW

Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MAC transmit data to be routed to

the MAC receive data path.

Setting this bit may cause the descrambler to lose synchronization

and produce a 500 µs “dead time” before any valid data will appear

at the MII receive outputs.

SPEED SELECTION LSB

Strap, RW

Speed Select (Bits 6, 13):

When auto-negotiation is disabled writing to this bit allows the port

speed to be selected.

11 = Reserved

10 = 1000 Mbps

1 = 100 Mbps

0 = 10 Mbps

AUTO-NEGOTIATION ENABLE

Strap, RW

Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are

ignored when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port

speed and duplex mode.

POWER DOWN

0, RW

Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is

enabled during a power down condition. This bit is ORd with the

input from the PWRDOWN_INT pin. When the active low

PWRDOWN_INT pin is asserted, this bit will be set.

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