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ASM330LXH 데이터시트(PDF) 42 Page - STMicroelectronics |
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ASM330LXH 데이터시트(HTML) 42 Page - STMicroelectronics |
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42 / 56 page ![]() Register description ASM330LXH 42/56 DocID027411 Rev 3 6.14 CTRL3_C (12h) Control register 3 (r/w). 100 00 200 12.5 100 01 200 24 100 10 200 50 100 11 200 55 101 00 400 18 101 01 400 23.5 101 10 400 45 101 11 400 86 110 00 800 28 110 01 800 34 110 10 800 46 110 11 800 78 111 00 n.a. n.a. 111 01 n.a. n.a. 111 10 n.a. n.a. 111 11 n.a. n.a. 1. Values in the table are indicative and can vary proportionally with the specific ODR value. Table 46. ODR and BW configuration setting (after LPF2) (continued) ODR_G [2:0] BW_G [1:0] ODR [Hz] Cutoff [Hz](1) Table 47. CTRL3_C register BOOT BDU 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. PP_OD SIM IF_ADD_INC BLE SW_RESET Table 48. CTRL3_C register description BOOT Reboot memory content. Default value: 0. (0: normal mode; 1: reboot memory content(1)) BDU Block Data Update. Default value: 0. (0: continuous update; 1: output registers not updated until MSB and LSB have been read) PP_OD Push-Pull/Open-Drain selection on INT pad. Default value: 0. (0: push-pull mode; 1: open drain mode) SIM SPI Serial Interface Mode selection. Default value: 0. (0: 4-wire interface; 1: 3-wire interface). IF_ADD_INC Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value: 1. (0: disabled; 1: enabled) |
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