LED2472GQTR datasheet(22/39 Pages) STMICROELECTRONICS

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Digital blocks

LED2472G

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DocID024620 Rev 3

Timings for shutdown and wakeup are present in the dynamic features table. While the auto

power shutdown is active, the device ignores any other command except channel power-on.

8.6

SDO delay (CFG 7)

Normally, on SDO terminals data is shifted out at the rising edge of the CLK signal with a

propagation delay of about 15 ns [signal (1) in Figure 11]. The device provides the possibility

to shift data out also at the falling edge of the CLK signal with a propagation delay of few ns

[signal (2) in Figure 11]. This feature can be activated by setting to “1” the bit CFG-7 of the

configuration register. The default setting for this bit is “0”, hence the SDO delay is not

activated by default. This feature is particularly useful when multiple devices are connected

in daisy chain configuration with non-matched delays between the CLK and SDO data paths

(board routing).

Figure 11. SDO Delay

8.7

Gradual output delay (CFG 8)

The gradual output delay consists in turning on gradually the current generators, avoiding

turning on all channels at the same time. This feature prevents large inrush current and

reduces the bypass capacitor values. The fixed delay time can be activated by bit CFG-8 of

the configuration register, and the typical delay is 10 ns for each group of 8 outputs R, G, B

(e.g. R1, G1, B1 has no delay, R2, G2, B2 has 10 ns of delay and R3, G3, B3, has 20 ns

delay, and so on), as described in Table 10.

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