LNBH26LSPQR datasheet(21/33 Pages) STMICROELECTRONICS

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LNBH26LS

I²C interface protocol

DocID025504 Rev 1

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7.3

Data registers

The DATA 1..4 registers can be addressed both to write and read mode. In read mode they

return the last writing byte status received in the previous write transmission.

The following tables provide the register address values of DATA 1..4 and a function

description of each bit.

Table 6: DATA 1 (read/write register. Register address = 0X2)

Bit

Name

Value

Description

Bit 0

(LSb)

VSEL1-

0/1

Channel A

output voltage selection bits.

(Refer to Table 13: "Output voltage selection table (data1

Bit 1

VSEL2-

0/1

Bit 2

VSEL3-

0/1

Bit 3

VSEL4-

0/1

Bit 4

VSEL1-

0/1

Channel B

output voltage selection bits.

(Refer to Table 13: "Output voltage selection table (data1

Bit 5

VSEL2-

0/1

Bit 6

VSEL3-

0/1

Bit 7

(MSb)

VSEL4-

0/1

N/A = reserved bit.

All bits reset to “0” at power-on.

Table 7: DATA 2 (read/write register. Register address = 0X3)

Bit

Name

Value

Description

Bit 0

(LSb)

TEN A

22 kHz tone enabled. Tone output controlled by the DSQIN

22 kHz tone output disabled

Bit 1

N/A

Reserved. Keep to “0”.

Bit 2

EXTM-

DSQIN input pin is set to receive external 22 kHz TTL signal

source

DSQIN input pin is set to receive external DiSEqC envelope

TTL signal

Bit 3

N/A

Reserved. Keep to “0”.

Bit 4

TEN-B

22 kHz tone enabled. Tone output controlled by the DSQIN

22 kHz tone output disabled

Bit 5

N/A

Reserved. Keep to

“0”.

Bit 6

EXTM-

DSQIN input pin is set to receive external 22 kHz TTL signal

source

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