POWERSTEP01TR datasheet(49/92 Pages) STMICROELECTRONICS

49 / 92 page

DocID025022 Rev 5

49/92

powerSTEP01

Serial interface

The integrated 8-bit serial peripheral interface (SPI) is used for a synchronous serial

communication between the host microprocessor (always master) and the device (always

slave).

The SPI uses chip select (CS), serial clock (CK), serial data input (SDI) and serial data

output (SDO) pins. When CS is high the device is unselected and the SDO line is inactive

(high impedance).

The communication starts when CS is forced low. The CK line is used for synchronization of

data communication.

All commands and data bytes are shifted into the device through the SDI input, most

significant bit first. The SDI is sampled on the rising edges of the CK.

All output data bytes are shifted out of the device through the SDO output, most significant

bit first. The SDO is latched on the falling edges of the CK. When a return value from the

device is not available, an all zero byte is sent.

After each byte transmission the CS input must be raised and be kept high for at least tdisCS

in order to allow the device to decode the received command and put the return value into

the shift register.

All timing requirements are shown in Figure 25 (see Section 3 on page 12 for values).

Multiple devices can be connected in daisy chain configuration, as shown in Figure 26.

Figure 25. SPI timings diagram

AM12837v1

SDI

SDO

MSB

LSB

N-1

N-2

MSB

HiZ

N-1

N-2

tsetCS

tenSDO

tsetSDI

tholSDI

tvSDO

tholSDO

trCK

tfCK

thCK

tlCK

tdisSDO

tholCS

tdisCS

MSB

POWERSTEP01TR 데이터시트(PDF) 49 Page - STMicroelectronics

POWERSTEP01TR 데이터시트(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL