Pad

Zeros

1

2

3

5

4

6

10

11

12

1

MSB−1 MSB−2 MSB−3 MSB−4 MSB−5

MSB−8 MSB−9

LSB+1

LSB

Hi−Z State

D6

D5

D4

D3

D2

D1

D0

D7

8

7

9

MSB−6 MSB−7

D7

MSB

MSB

16

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Access Cycle

Sample Cycle

Channel

Address

A/D Conversion Interval

Output Data

Format

Previous Conversion Data

Initialize

Initialize

CS

I/O

CLOCK

DATA

OUT

DATA IN

EOC

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

MSB

1

2

3

5

4

6

1

MSB−1 MSB−2 MSB−3 MSB−4 MSB−5

LSB+1

LSB

2

3

D6

D5

8

7

D7

Low Level

MSB

D6

D5

D4

D3

D2

D1

D0

D7

MSB−2

MSB−1

4

5

6

7

D4

D3

MSB−4

MSB−3

D2

D1

MSB−6

MSB−5

Access

Cycle

Sample Cycle

Channel

Address

A/D Conversion Interval

Output Data

Format

Previous Conversion Data

Initialize

Initialize

CS

I/O

CLOCK

DATA

OUT

DATA IN

EOC

TLV2553

www.ti.com

SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 4. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First

Figure 5. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First

Copyright © 2001–2015, Texas Instruments Incorporated

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