I3G4250D datasheet(39/43 Pages) STMICROELECTRONICS

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I3G4250D

7.20

INT1_THS_YL (35h)

7.21

INT1_THS_ZH (36h)

7.22

INT1_THS_ZL (37h)

7.23

INT1_DURATION (38h)

The D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration

steps and maximum values depend on the ODR chosen.

The WAIT bit has the following meaning:

Wait = ’0’: the interrupt falls immediately if the signal crosses the selected threshold.

Wait = ’1’: if the signal crosses the selected threshold, the interrupt falls only after the

duration has counted a number of samples at the selected data rate, written into the

duration counter register.

Table 58. INT1_THS_YL register

THSR7

THSY6

THSY5

THSY4

THSY3

THSY2

THSY1

THSY0

Table 59. INT1_THS_YL description

THSY7 - THSY0

Interrupt threshold. Default value: 0000 0000

Table 60. INT1_THS_ZH register

THSZ14

THSZ13

THSZ12

THSZ11

THSZ10

THSZ9

THSZ8

Table 61. INT1_THS_ZH description

THSZ14 - THSZ8

Interrupt threshold. Default value: 0000 0000

Table 62. INT1_THS_ZL register

THSZ7

THSZ6

THSZ5

THSZ4

THSZ3

THSZ2

THSZ1

THSZ0

Table 63. INT1_THS_ZL description

THSZ7 - THSZ0

Interrupt threshold. Default value: 0000 0000

Table 64. INT1_DURATION register

WAIT

Table 65. INT1_DURATION description

WAIT

WAIT enable. Default value: 0 (0: disable; 1: enable)

D6 - D0

Duration value. Default value: 000 0000

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