LSM6DS3TR datasheet(30/100 Pages) STMICROELECTRONICS

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Functionality

LSM6DS3

30/100

DocID026899 Rev 8

5.4

FIFO

The presence of a FIFO allows consistent power saving for the system since the host

processor does not need continuously poll data from the sensor, but it can wake up only

when needed and burst the significant data out from the FIFO.

LSM6DS3 embeds 8 kbytes data FIFO to store the following data:



gyroscope



accelerometer



external sensors



step counter and timestamp



temperature

Writing data in the FIFO can be configured to be triggered by the:

- accelerometer/gyroscope data-ready signal; in which case the ODR must be lower than or

equal to both the accelerometer and gyroscope ODRs;

- sensor hub data-ready signal;

- step detection signal.

In addition, each data can be stored at a decimated data rate compared to FIFO ODR and it

is configurable by the user, setting the registers FIFO_CTRL3 (08h) and FIFO_CTRL4

(09h). The available decimation factors are 2, 3, 4, 8, 16, 32.

Programmable FIFO threshold can be set in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)

using the FTH [11:0] bits.

To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2

(3Bh), FIFO_STATUS3 (3Ch), FIFO_STATUS4 (3Dh)) can be read to detect FIFO overrun

events, FIFO full status, FIFO empty status, FIFO threshold status and the number of

unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2

pads of these status events, the configuration can be set in INT1_CTRL (0Dh) and

INT2_CTRL (0Eh).

FIFO buffer can be configured according to five different modes:

– Bypass mode

– FIFO mode

– Continuous mode

– Continuous-to-FIFO mode

– Bypass-to-continuous mode

Each mode is selected by the FIFO_MODE_[2:0] in FIFO_CTRL5 (0Ah) register. To

guarantee the correct acquisition of data during the switching into and out of FIFO mode,

the first sample acquired must be discarded.

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