TUSB8041RGCT datasheet(19/48 Pages) TI1

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TUSB8041

www.ti.com

SLLSEE4D – JUNE 2014 – REVISED JANUARY 2016

Table 15. Bit Descriptions – Device Configuration Register (continued)

Ganged. This bit is loaded at the de-assertion of reset with the value of

the GANGED/SMBA2/HS_UP pin.

0 = When fullPwrMgmtz = 0, each port is individually power switched

and enabled by the PWRCTL[4:1]/BATEN[4:1] pins

1 = When fullPwrMgmtz = 0, the power switch control for all ports is

ganged

ganged and enabled by the PWRCTL[4:1]/BATEN1 pin

When the TUSB8041 is in I2C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

Full Power Management. This bit is loaded at the de-assertion of reset

with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.

0 = Port power switching status reporting is enabled

1 = Port power switching status reporting is disabled

fullPwrMgmtz

When the TUSB8041 is in I2C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

Reserved. This field is reserved and should not be altered from the

RSVD

default.

RSVD

Reserved. This field is reserved and returns 0 when read.

8.5.8 Battery Charging Support Register

Table 16. Register Offset 6h

Bit No.

Reset State

Table 17. Bit Descriptions – Battery Charging Support Register

Bit

Field Name

Access

Description

7:4

RSVD

Reserved. Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the

downstream port implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

Each bit corresponds directly to a downstream port, i.e. batEn0

3:0

batEn[3:0]

corresponds to downstream port 1, and batEN1 corresponds to

downstream port 2.

The default value for these bits are loaded at the de-assertion of reset

with the value of PWRCTL/BATEN[3:0].

When in I2C/SMBus mode the bits in this field may be over-written by

EEPROM contents or by an SMBus host.

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