DocID028369 Rev 1

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STHVDAC-256MTG

Devices operating modes

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Figure 5. HVDAC state diagram

4.4

Device reset

Power-On Reset is implemented on the VI/O supply input, ensuring the HVDAC will be reset

to default mode once VI/O supply line rises above a given threshold (typically 1V). This

trigger will force all registers to their default value.

Device Reset is also implemented as defined in the MIPI RFFE specification. Setting

PWR_MODE bits to 01b will force the device to reset all registers to their default value, and

then automatically switch the device into low power mode.

A Soft Reset is implemented using register #26 MSB. Setting this bit will reset all registers to

their default values, except PM_TRIG register (reg #28) and device USID (reg #31).

4.5

RFFE serial interface

The HVDAC is fully controlled through RFFE serial interface (DATA, VIO, CLOCK).

This interface is further described in the next sections of this document and is made

compliant to the MIPI Alliance Specification for RF Front End control Interface version 1.10 -

26 July 2011 (see Figure 12 and Figure 13).

Sequence Start Condition (SSC): One rising edge followed by falling edge on DATA while

CLK remains at logic level low. This is used by the Master to identify the start of a Command

frame.

Parity (P): Each frame shall end with a single parity bit. The parity bit shall be driven such

that the total number of bits in the frame that are driven to logic level one, including the

parity bit, is odd.