STM32F446VE datasheet(109/201 Pages) STMICROELECTRONICS

109 / 201 page

DocID027107 Rev 5

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STM32F446xC/E

Electrical characteristics

174

IDD(PLL)(4)

PLL power consumption on VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLL)(4)

PLL power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed based on test during characterization.

Table 43. Main PLL characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 44. PLLI2S (audio PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLI2S_IN

PLLI2S input clock(1)

-0.95(2)

12.10

MHz

fPLLI2S_OUT

PLLI2S multiplier output clock

216

MHz

fVCO_OUT

PLLI2S VCO output

100

432

MHz

tLOCK

PLLI2S lock time

VCO freq = 100 MHz

200

µs

VCO freq = 432 MHz

100

300

Jitter(3)

Master I2S clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

-400

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed based on test during characterization.

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