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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VS6663CC 데이터시트(PDF) 17 Page - STMicroelectronics |
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VS6663CC 데이터시트(HTML) 17 Page - STMicroelectronics |
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17 / 63 page  Doc ID028526 Rev 1 17/63 VS6663CC Functional description 46 3.2.2 Power-down procedure The power-down sequence timing constraints are shown in Table 7. Table 7. Power-down sequence timing constraints for CSI2 communications Symbol Parameter Minimum Maximum Units t8 Last I2C transaction to software standby - 1 frame t9 Last I2C transaction or MIPI frame end to XSHUTDOWN falling 512 - clock cycles t10 XSHUTDOWN to VANA/VDIG falling XSHUTDOWN must fall at the same time as, or earlier than, both power supplies (VDIG and VANA) t11 VANA to VDIG or VDIG to VANA falling VANA and VDIG may fall in any order, the rising separation can vary from 0 ns to indefinite |
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