SAB80C166 datasheet(13/52 Pages) INFINEON

13 / 52 page

SAB 80C166/83C166

Semiconductor Group

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal

program execution), the SAB 80C166 is capable of reacting very fast to the occurrence of non-

deterministic events.

The architecture of the SAB 80C166 supports several mechanisms for fast and flexible response to

service requests that can be generated from various sources internal or external to the

microcontroller. Any of these interrupt requests can be programmed to being serviced by the

Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and

a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU

activity to perform a PEC service. A PEC service implies a single byte or word data transfer between

any two memory locations with an additional increment of either the PEC source or the destination

pointer. An individual PEC transfer counter is implicity decremented for each PEC service except

when performing in the continuous transfer mode. When this counter reaches zero, a standard

interrupt is performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data, or for

transferring A/D converted results to a memory table. The SAB 80C166 has 8 PEC channels each

of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an

interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each

source can be programmed to one of sixteen interrupt priority levels. Once having been accepted

by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For

the standard interrupt processing, each of the possible interrupt sources has a dedicated vector

location.

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number.

The following table shows all of the possible SAB 80C166 interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

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