54F410DM datasheet(2/8 Pages) NSC

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Unit LoadingFan Out

54F74F

Pin Names

Description

Input IIH IIL

HIGHLOW

Output IOH IOL

A0–A3

Address Inputs

1010

20 mA b06 mA

D0–D3

Data Inputs

1010

20 mA b06 mA

Chip Select Input (Active LOW)

1020

20 mA b12 mA

Output Enable Input (Active LOW)

1010

20 mA b06 mA

Write Enable Input (Active LOW)

1010

20 mA b06 mA

Clock Input (Outputs Change on

LOW-to-HIGH Transition)

1020

20 mA b12 mA

Q0–Q3

TRI-STATE Outputs

15040 (333)

3 mA24 mA (20 mA)

Functional Description

Write Operation

When the three control inputs Write En-

able (WE) Chip Select (CS) and Clock (CP) are LOW the

information on the data inputs (D0–D3) is written into the

memory location selected by the address inputs (A0–A3) If

the input data changes while WE CS and CP are LOW the

contents of the selected memory location follow these

changes provided setup and hold time criteria are met

Read Operation

Whenever CS is LOW and CP goes from

LOW-to-HIGH the contents of the memory location select-

ed by the address inputs (A0–A3) are edge-triggered into

the Output Register

The (OE) input controls the output buffers When OE is

HIGH the four outputs (Q0–Q3) are in a high impedance or

OFF state when OE is LOW the outputs are determined by

the state of the Output Register

Block Diagram

TLF9538 – 4

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